The present invention relates to a three-state output circuit.
The three-state output circuit is very useful for fabricating memory circuits or logic circuits, for the purpose of simplifying the circuit constructions thereof. The wording "three-state" represents, firstly a normal "H" (high) level state of the output signal, secondly a normal "L" (low) level state of the output signal and thirdly a high-impedance state "Z" of the output stage. Thus, when the three-state output circuit is caused to be active, this circuit produces, from its output stage, an "H" level output signal or an "L" level output signal in accordance with the logic of an input signal applied thereto. Contrary to this, when the three-state output circuit is caused to be non-active, the output stage thereof becomes the high-impedance state. In other words, the output impedance of the three-state circuit becomes high. This high-impedance state allows, in a memory circuit system, time-sharing of a common bus line. This high-impedance state also allows, in the logic circuit system, construction of a simple wired-OR logic circuit.
The three-state output circuit is divided, as a whole, into a first stage, a second stage and a third stage. The first stage functions as an input circuit which receives an input logic signal having a logic "1" or "0". The third stage corresponds to the aforesaid output stage of the three-state output circuit. The second stage functions as a control circuit which causes the third stage, that is the output stage, to be the high-impedance state "Z" or the normal state, in which normal state the output stage produces an "H" or an "L" level output signal in accordance with the logic of said input logic signal applied to the first stage, that is the input circuit.
As will be explained hereinafter, when the three-state output circuit is caused to be active, the control circuit operates to absorb a current from a power supply line via the output stage and also via the input circuit. The current to be absorbed from the power line to the control circuit is considerably large, in the case where the control circuit is employed as a chip enable circuit in the memory device. This is because the chip enable circuit is common to all the four or eight output stages, when the memory device is constructed as a 4-bit output memory device or an 8-bit output memory device, respectively. In this case, said current to be adsorbed from the power supply line and fed to the control circuit, that is the chip enable circuit, is called a chip enable current. Since the chip enable circuit is common to all the said output stages, the level of the magnitude of the chip enable current becomes four times as high as the level of the magnitude of the current to be absorbed through each said input circuit and output stage, when operating as the 4-bit output memory device, or eight times as high as the level of the magnitude of the current to be absorbed through each said input circuit and output stage, when operating as the 8-bit output memory device.
Consequently, the chip enable circuit, that is the control circuit, must be comprised of high power transistors and thereby the circuit pattern thereof becomes very large in size. Therefore, the amount of the parasistic capacitance is caused to be very large due to the creation of said large size circuit pattern. Further, since the chip enable current is very large, a chip enable line must be fabricated so as to be very wide in width thereof. Furthermore, since the chip enable current is common to all pairs of said input circuits and output stages and all these pairs are arranged side by side with a predetermined space between each two pairs, the length of the chip enable line becomes very long. Therefore, the amount of the stray capacitance is caused to be very large due to the existence of the very long and wide chip enable line. The above mentioned large amounts of both the parasistic capacitance and the stray capacitance apparently result in the fact that the operating speed of the three-state output circuit is reduced and, as a result, the operating speed of the memory device is reduced.